In a wireless data transmission scheme, in order to demodulate and decode an incoming signal it is generally necessary to synchronize the clock of an incoming signal with a local clock on the receiver. This requires the receiver to first determine a frequency offset of the incoming signal with respect to the local clock before it can begin demodulating in decoding the signal.
One way of determining a frequency offset involves performing autocorrelation on samples of the incoming signal and looking for maximum points. Based on the location of these maximum points, the receiver can determine a frequency offset value between the clock of the incoming signal and the receiver's local clock.
Once the frequency correction value is determined, the receiver can then proceed to a demodulation and decoding operation. During this operation, the receiver will perform correlation of the incoming signal with a known PN code to identify where the symbols (i.e., chips) are.
Conventional frequency offset estimation and demodulation/decoding operations are performed on I/Q data. When I/Q data is used, both correlation and autocorrelation require the receiver to perform complex multiplication. This complex multiplication is a complicated operation that requires significant circuitry to implement. Furthermore, as the amount of circuitry required increases, so too does the amount of power that circuitry uses, and the space required on a chip to form that circuitry.
In addition, conventional frequency offset estimation requires that multiple autocorrelation values be generated to determine a frequency offset estimate. Also, each autocorrelation value that must be calculated requires additional time and additional power.
Furthermore, conventional frequency offset estimation and demodulation/decoding operations are implemented using separate circuitry for each of these tasks. This serves to further increase the power requirements for a signal demodulator, as well as the required surface area of a chip required to contain the signal demodulator.
It would therefore be desirable to provide a signal demodulation circuit and method that is relatively simple in design, may require lower power than conventional demodulation circuits, may operate more quickly than conventional demodulation circuits, and may take up less space on a chip than conventional demodulation circuits.